1. Field of the Invention
The present invention generally relates to buffer access control circuits which are used to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address, and more particularly to a buffer access control circuit which uses a simple circuit construction to carry out a process of updating the address one by one when consecutively accessing the upper buffer and the lower buffer.
There exists a type of buffer which is divided into an upper buffer and a lower buffer which are assigned the same address. When consecutively accessing the upper buffer and the lower buffer of such a buffer, an access process is carried out by updating the address one by one and accessing data regions of the buffer indicated by the successively updated address. It is desirable that this access process can be realized by use of a simple circuit construction.
2. Description of the Related Art
The access process with respect to the buffer which is divided into the upper buffer and the lower buffer which are assigned the same address, includes a first access process with respect to the buffer formed by the upper buffer and the lower buffer, and a second access process with respect to the upper buffer and the lower buffer.
In the case of the second access process, the upper buffer may be specified again as the access destination after the upper buffer is accessed or, the lower buffer may be specified again as the access destination after the lower buffer is accessed. In this case, the access to the buffer is made without updating the address. On the other hand, in the first access process, when the lower buffer is specified as the access destination after the upper buffer is accessed or, when the upper buffer is specified as the access destination after the lower buffer is accessed, the access to the buffer is made by counting up the address by one.
A description will be given of an access to a 2-byte buffer having a 1-byte upper buffer 401 and a 1-byte lower buffer 402, by referring to FIGS. 1 through 4.
FIG. 1 shows a case where a write request is first issued to write a data A by specifying the lower buffer 402 as an access destination. In this case, the data A is written in the lower buffer 402 at a location {circle around (1)} specified by a present address, according to the algorithm described above. When a write request is then issued to write a data B by again specifying the lower buffer 402 as the access destination, the data B is written in the lower buffer 402 at the location {circle around (1)} according to the algorithm described above, thereby rewriting the previously written data A with the data B.
Similarly, FIG. 2 shows a case where a write request is first issued to write a data A by specifying the upper buffer 401 as an access destination. In this case, the data A is written in the upper buffer 401 at a location {circle around (2)} specified by a present address, according to the algorithm described above. When a write request is then issued to write a data B by again specifying the upper buffer 401 as the access destination, the data B is written in the upper buffer 401 at the location {circle around (2)} according to the algorithm described above, thereby rewriting the previously written data A with the data B.
On the other hand, FIG. 3 shows a case where a write request is first issued to write a data A by specifying the lower buffer 402 as an access destination. In this case, the data A is written in the lower buffer 402 at a location {circle around (1)} specified by a present address, according to the algorithm described above. When a write request is then issued to write a data B by specifying the upper buffer 401 as the access destination, the data B is written in the upper buffer 401 at the location {circle around (2)} according to the algorithm described above. Thereafter, the present address is counted up by one.
Next, when a write request is issued to write a data C by specifying the lower buffer 402 as the access destination, the data C is written in the lower buffer 402 at a location {circle around (3)} specified by the updated present address, according to the algorithm described above. In addition, when a write request is then issued to write the data C by specifying the upper buffer 401 as the access destination, the data C is written in the upper buffer 401 at the location {circle around (4)} specified by the updated present address, according to the algorithm described above.
Similarly, FIG. 4 shows a case where a write request is first issued to write a data A by specifying the upper buffer 401 as an access destination. In this case, the data A is written in the upper buffer 401 at the location {circle around (2)} specified by a present address, according to the algorithm described above. When a write request is then issued to write a data B by specifying the lower buffer 402 as the access destination, the data B is written in the lower buffer 401 at the location {circle around (1)} according to the algorithm described above. Thereafter, the present address is counted up by one.
Next, when a write request is issued to write a data C by specifying the upper buffer 401 as the access destination, the data C is written in the upper buffer 401 at the location {circle around (4)} specified by the updated present address, according to the algorithm described above. In addition, when a write request is then issued to write the data C by specifying the lower buffer 402 as the access destination, the data C is written in the lower buffer 402 at the location {circle around (3)} specified by the updated present address, according to the algorithm described above.
FIG. 5 is a system block diagram showing an example of a conventional buffer access control circuit which carries out the access process of the buffer 400 described above.
The buffer access control circuit shown in FIG. 5 includes D-type flip-flop circuits 100, 101 and 105, an AND circuit 102, a check signal generating circuit 103, an address counter (ADR. CTR.) circuit 104, and a delay circuit 106 which are connected as shown, with respect to the buffer 400. The flipflop 100 latches a power supply voltage Vcc at a falling edge of a lower buffer access signal LBA which has a low level when there is an instruction to access the lower buffer 402. The flip-flop circuit 101 latches the power supply voltage Vcc at a falling edge of an upper buffer access signal UBA which has a low level when there is an instruction to access the upper buffer 401. The AND circuit 102 obtains a logical product AND of data det-L and det-H latched by the flip-flop circuits 100 and 101. The check signal generating circuit 103 generates a check signal chk which has a low level when one of the lower buffer access signal LBA and the upper buffer access signal UBA has a low level. The address counter circuit 104 inputs an output signal andO of the AND circuit 102 at a rising edge of the check signal chk which is applied to the clock (CK) input of the address counter circuit 104, and counts up a counted value, which becomes the buffer address, when the output signal andO of the AND circuit 102 has a high level. The flip-flop (FF) circuit 105 latches the output signal andO of the AND circuit 102 at the rising edge of the check signal chk, and outputs an inverted output signal. The delay circuit 106 delays the inverted output signal of the flip-flop circuit 105, and supplies a clear signal CL to clear terminals of the flip-flop circuits 100, 101 and 105. Each of the flip-flop circuits 100, 101 and 105 carries out a clear process at a rising edge of the clear signal CL input to the clear terminal thereof.
According to the buffer access control circuit having the construction shown in FIG. 5, when the lower buffer 402 is specified as the access destination and the upper buffer 401 is next specified as the access destination, the AND circuit 102 outputs a high-level signal andO at the falling edge of the upper buffer access signal UBA, as shown in a time chart of FIG. 6.
In response to this high-level output signal andO of the AND circuit 102, the address counter circuit 104 counts up the counted value by one at the rising edge of the check signal chk which rises at the rising edge of the upper buffer access signal UBA. In FIG. 6, ADR indicates the counted value of the address counter circuit 104. On the other hand, in response to the high-level output signal andO of the AND circuit 102, the inverted output signal of the flip-flop circuit 105 makes a transition from a high level to a low level at the rising edge of the check signal chk.
The delay circuit 106 delays the inverted output signal of the flip-flop circuit 105 by a delay time A, so as to output the clear signal CL which makes a transition to a low level after the delay time A from the rising edge of the upper buffer access signal UBA. Each of the flip-flop circuits 100, 101 and 105 clears the held signal from the high level to the low level in response to this clear signal CL.
Furthermore, the delay circuit 106 delays the inverted output signal of the flip-flop circuit 105 by the delay time xcex94, so as to output the clear signal CL which makes a transition to a high level after the delay time xcex94 from the falling edge of the output signal andO of the AND circuit 102, thereby returning the buffer access control circuit to the state before the upper buffer access signal UBA was issued.
The time chart of FIG. 6 describes the case where the lower buffer 402 is specified as the access destination and the upper buffer 401 is next specified as the access destination. The operation of the circuit shown in FIG. 5 is similar to that described above in the case where the upper buffer 401 is specified as the access destination and the lower buffer 402 is next specified as the access destination. FIG. 7 is a time chart for this case where the upper buffer 401 is specified as the access destination and the lower buffer 402 is next specified as the access destination. In FIG. 7, those parts which are the same as those corresponding parts in FIG. 6 are designated by the same reference numerals, and a description thereof will be omitted.
Therefore, the conventional buffer access control circuit is provided with the flip-flop circuit 100 which carries out a latch operation using the lower buffer access signal LBA as a latch signal, the flip-flop circuit 101 which carries out a latch operation using the upper buffer access signal UBA as a latch signal, and the AND circuit 102 which obtains the logical product AND of the latched data det-L and det-H from the two flip-flop circuits 100 and 101. Every time a buffer access signal is issued, a reference is made to the output signal andO of the AND circuit 102 to detect whether or not the upper buffer 401 and the lower buffer 402 are consecutively specified as the access destination. In addition, when it is detected that the upper buffer 401 and the lower buffer 402 are consecutively specified as the access destination, the delay time xcex94 of the delay circuit 106 is used to clear the latched data det-L and det-H of the two flip-flop circuits 100 and 101 after this detection.
According to the conventional buffer access control circuit, the delay circuit 106 is essential to detect whether or not the upper buffer 401 and the lower buffer 402 are consecutively specified as the access destination.
In other words, the flip-flop circuits 100 and 101 carry out the latch operations when the upper buffer 401 and the lower buffer 402 are consecutively specified as the access destination, and when this is detected in synchronism with the check signal chk output from the check signal generating circuit 103, it is necessary to clear the latched data of the flip-flop circuits 100 and 101 in order to carry out the next detection.
The delay time xcex94 generated by the delay circuit 106 is used to carry out the clear process after the delay time xcex94 elapses from the time when it is detected that the two flip-flop circuits 100 and 101 have started the latch operations. This is the reason why the delay circuit 106 is essential.
However, when the delay circuit 106 is provided as in the conventional buffer access control circuit to realize the delay time xcex94, there is a problem associated with variations in the delay time xcex94 in that an adjusting process becomes necessary.
In other words, if the delay time xcex94 is too small, the flip-flop circuits 100 and 101 will be cleared before the detection is made to determine whether or not the flip-flop circuits 100 and 101 have started the latch operations. On the other hand, if the delay time xcex94 is too large, the next buffer access signal will be issued before the latched data of the flip-flop circuits 100 and 101 are cleared.
Accordingly, it is a general object of the present invention to provide a novel and useful buffer access control circuit in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a buffer access control circuit which is used to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address, and uses a simple circuit construction to carry out a process of updating the address one by one when consecutively accessing the upper buffer and the lower buffer.
Still another object of the present invention is to provide a buffer access control circuit for carrying out a process of updating an address one by one when consecutively accessing an upper buffer and a lower buffer as an access destination with respect to a buffer which is divided into the upper buffer and the lower buffer which are assigned the same address. In the buffer access control circuit, a detection circuit detects whether or not the upper buffer and the lower buffer are consecutively specified as the access destination, by storing levels when the upper buffer or the lower buffer is specified as the access destination, based on a corresponding relationship of a state where one of a high level and a low level is specified as the access destination and a state where the other of the high level and the low level is not specified as the access destination. A modifying circuit modifies a definition which prescribes the corresponding relationship to an opposite definition, when the detection circuit detects that the upper buffer and the lower buffer are consecutively specified as the access destination. According to the buffer access control circuit of the present invention, it is possible to carry out the process of updating the address one by one, without the use of a delay circuit which was essential in the conventional buffer access control circuit. For this reason, it is unnecessary to carry out a process of adjusting a delay time of the delay circuit, and the buffer access control circuit can be produced without the need for the delay time adjusting process.
A further object of the present invention is to provide a buffer access control circuit for carrying out a process of updating an address one by one when consecutively accessing an upper buffer and a lower buffer as an access destination with respect to a buffer which is divided into the upper buffer and the lower buffer which are assigned the same address. In the latter buffer access control circuit, a first latch circuit latches data in response to a lower buffer access signal for accessing the lower buffer and a second latch circuit latches the data in response to an upper buffer access signal for accessing the upper buffer. A detection circuit detects whether or not data latched by the first latch circuit and data latched by the second latch circuit match, and a modifying circuit inputs the data which indicates one of a high level and a low level to the first and second latch circuits, and modifies a level of the data to an inverted level when one of the upper and lower buffer access signals is generated and the detection circuit detects the match. According to the latter buffer access control circuit of the present invention, it is possible to carry out the process of updating the address one by one, without the use of a delay circuit which was essential in the conventional buffer access control circuit. For this reason, it is unnecessary to carry out a process of adjusting a delay time of the delay circuit, and the buffer access control circuit can be produced without the need for the delay time adjusting process.
Another object of the present invention is to provide a memory unit comprising a buffer divided into an upper buffer and a lower buffer which are assigned the same address, and a buffer access control circuit carrying out a process of updating an address one by one when consecutively accessing the upper buffer and the lower buffer as an access destination with respect to the buffer. In the buffer access control circuit, a detection circuit detects whether or not the upper buffer and the lower buffer are consecutively specified as the access destination, by storing levels when the upper buffer or the lower buffer is specified as the access destination, based on a corresponding relationship of a state where one of a high level and a low level is specified as the access destination and a state where the other of the high level and the low level is not specified as the access destination. A modifying circuit modifies a definition which prescribes the corresponding relationship to an opposite definition, when the detection circuit detects that the upper buffer and the lower buffer are consecutively specified as the access destination. According to the memory unit of the present invention, it is possible to carry out the process of updating the address one by one, without the use of a delay circuit which was essential in the conventional buffer access control circuit. For this reason, it is unnecessary to carry out a process of adjusting a delay time of the delay circuit, and the buffer access control circuit can be produced without the need for the delay time adjusting process.
Still another object of the present invention is to provide a memory unit comprising a buffer divided into an upper buffer and a lower buffer which are assigned the same address, and a buffer access control circuit carrying out a process of updating an address one by one when consecutively accessing the upper buffer and the lower buffer as an access destination with respect to the buffer. In the buffer access control circuit, a first latch circuit latches data in response to a lower buffer access signal for accessing the lower buffer and a second latch circuit latches the data in response to an upper buffer access signal for accessing the upper buffer. A detection circuit detects whether or not data latched by the first latch circuit and data latched by the second latch circuit match. A modifying circuit inputs the data which indicates one of a high level and a low level to the first and second latch circuits and modifies a level of the data to an inverted level when one of the upper and lower buffer access signals is generated and the detection circuit detects the match. According to the latter memory unit of the present invention, it is possible to carry out the process of updating the address one by one, without the use of a delay circuit which was essential in the conventional buffer access control circuit. For this reason, it is unnecessary to carry out a process of adjusting a delay time of the delay circuit, and the buffer access control circuit can be produced without the need for the delay time adjusting process.